frmv3

Tests of the Bus Pirate logic analyzer went so well that we’re rolling it into firmware v3 preview for all hardware. In addition to the features described in the last post, the updated logic analyzer supports configurable sample size (up to 4096), speed (10Hz-~1MHz), and triggers.

There’s a few other goodies tucked into the preview release. The transparent UART bridge now clears buffer overruns automatically and turns off the MODE LED to signal the error, read more in the updated UART mode guide. Code controlling¬† frequency measurement and pulse-width modulation on the AUX pin received a minor overhaul.

v3.0 also includes the new raw 2- and 3-wire binary access mode. This mode can be used to dump and program a SLE4442 smartcard from a script. You can also now access the ADC and PWM from Perl, Python, etc. scripts in binary mode.

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