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Seeed Studio is working on a probe cable for the Open Logic Sniffer. We’ll give you an update as soon as we hear more.

You can try building your own cable with some cheap probes from Deal Extreme (~$3 for 10). The trick will be finding a 1×9 row connector, if you know of any sources please share them in the comments.

The Open Logic Sniffer is currently available for preorder at Seeed Studio for $45, including worldwide shipping.

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We spotted an Open Logic Sniffer in Adafruit’s weekly Ask an Engineer Chat. It looks like they’re soldering it up on a reflow plate. We like the warning that the reflow plate may be a hot surface.

Jack has a bunch of Open Logic Sniffer tutorial and testing videos at the Gadget Factory. There’s also a demo on YouTube, and a high quality screencast.

The Open Logic Sniffer is currently available for preorder at Seeed Studio for $45, including worldwide shipping.

We’ve been working on an open source logic analyzer with Jack Gassett of the Gadget Factory. The project was known by the code name ‘SUMP-PUMP’, but you helped suggest a name. There were lots of great suggestions in the comments and the forum. Thank you.

LukeS suggested the name Logic Sniffer. He’ll get one of the first Open Logic Sniffers shipped. Thanks LukeS!

The Open Logic Sniffer is currently available for preorder at Seeed Studio for $45, including worldwide shipping.

Openbench Logic Sniffer is an open source logic analyzer. It’s designed to support the SUMP logic analyzer software at the lowest possible cost. Download the source and design files from the Gadget Factory project page.

This project started in the comments on a post. Initial circuit design, PCB layout, development, and testing continued in the forum under the code name Project SUMP PUMP. Many, many people contributed ideas and advice, the Gadget Factory and Dangerous Prototypes coordinated circuit development and routed the PCB. We borrowed heavily from the Gadget Factory’s Butterfly Platform.

The Open Logic Sniffer is a purpose-built logic analyzer board designed to be low cost but high speed. It sacrifices a lot of the features you’d look for in a full-scale development board to achieve our primary goals:

  • 70MHz+ sample speeds
  • 32 channels
  • 16 buffered, 5volt tolerant channels
  • USB interface, USB powered
  • USB upgradable everything
  • Make it as DIY as possible
  • Make it as open source as possible
  • $30-$40 price range

We didn’t quite hit our initial price range, but we got really close.

You can get your own assembled Open Logic Sniffer at Seeed Studio for $45, including worldwide shipping. Continue reading about the design and collaboration below.

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We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. The project is currently known by the code name ‘SUMP-PUMP’, but you can help suggest a name. The design incorporates elements of the Butterfly platform, which is available now at the Gadget Factory.

On Wednesday we offered a free SUMP PUMP to the developer of a command line utility that could replace our Perl script ROM uploader. Michal Demin completed the challenge in less than 24hours. Piotr and Ipenguin helped with patches for the Mac. Congratulations, and thanks for the hard work!

Michal will receive a preview SUMP PUMP. You can try the app here.

We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. The project is currently known by the code name ‘SUMP-PUMP’, but you can help suggest a name. The design incorporates elements of the Butterfly platform, which is available now at the Gadget Factory.

Update: Michal Demin completed this challenge in less than 24hours. Congratulations!

Here’s your chance to get a SUMP PUMP for free, maybe even a preview unit. We need command line utilities to update the SUMP PUMP FPGA image from Windows, Mac, and Linux. We’re currently using a Perl script, but this is too much hassle for end users. If you develop the best console update utility, we’ll send you the SUMP PUMP hardware.

The update is done over a virtual serial port using a simple protocol. Ideally, the utility would load Intel HEX files directly, but we have raw binary blobs too. The utility must compile on all major platforms (Windows, MacOSX, and Linux). Piotr’s Pirate-Loader utility source code should have everything you need to get started. Here’s a development thread in the forum.

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We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. The project is currently known by the code name ‘SUMP-PUMP’, but you can help suggest a name. The design incorporates elements of the Butterfly platform, which is available now at the Gadget Factory.

Jack finished a bunch of tests on the first SUMP PUMP build, check out the pictures and screen shots.

We’ve got the PIC firmware working, but there’s still an issue with the bootloader. You can follow our progress and make suggestions in the forum.

Today we completed an initial PIC firmware for the open source logic analyzer. The PIC has two operating modes: a serial bridge for SUMP to talk to the client on the FPGA, and a ROM programmer that updates the AT45DB041D flash chip with new logic for the FPGA. There’s still some bugs, but the design is coming together. Give your suggestions and follow our progress in the forum.

Major to dos:

  • Finish the USB bootloader port to 18f24j50
  • Clean and comment the PIC source
  • Clean up the PERL updater scripts

Please join us in the forum to discuss a digital sampling oscilloscope add-on for the open source logic analyzer (currently referred to as project SUMP PUMP). Our general goal is to design an inexpensive expansion board that samples analog voltages at 50MHz+.

The combination of a logic analyzer and sampling oscilloscope is a powerful debugging tool. The logic analyzer displays changes in signal states, the oscilloscope reveals how clean the transitions are.

We’re in the process of choosing a parallel ADC chip and discussing analog front-end designs. Feel free to make requests, suggestions, or just follow along.

We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. Gerbers will go to the board house before the end of this week.

Until now we’ve called this project by the codename ‘SUMP PUMP’, because it’s a data pump for the open source SUMP logic analyzer client. This name is far to clever though, because SUMP infringes on the name of the original project, and it won’t index well in search engines.

We’d like to hear your suggestions for a name for this project. If we choose your name, we’ll send you the final hardware for free. Post your suggestions here, or in the forum.

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A few months ago we started working with the Gadget Factory to build an open source logic analyzer. After a very successful collaboration, we’re almost ready to order the first PCBs. Click here for a large PCB image [PNG].

The draft device has 16 buffered (5volt tolerant) input channels, and 16 unbuffered I/O channels on a wing header.  The PC connection is USB 2.0 with a PIC18F24J50 microcontroller. Both the PIC and the FPGA firmware will be USB upgradable.

You can follow our most recent progress in the forum. Uwe’s block diagram of the final design follows.

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Merve is working on an Arduino-driven logic analyzer design in the Arduino Forum. It uses logic chips to drive SRAM memory during acquisition, the Arduino then dumps samples from the SRAM via a shift register.

We’re really interested in the result of this design. We once attempted a logic chip-based analyzer, but the design got complicated at high speeds because of the need for 16bit+ synchronous counters to drive the SRAM. Instead, we moved to CPLDs to try and squeeze all the logic ICs into a single, reprogrammable chip.

Several readers submitted a link to this post, thanks for the tip!

Development of the open source logic analyzer, first discussed here, has progressed rapidly in the forum.

We’ve looked at cost estimates, Uwe made some excellent block diagrams, and Jack has already added a basic layout to his SVN.

Read our goals and specs after the break.

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We’re really excited to be joined by Jack Gassett, developer of the Butterfly FPGA platform, to prototype an open source, high-speed, low-cost logic analyzer. This effort grew out of a bunch of great comments on a post about open source logic analyzer clients.

Share your ideas for the logic analyzer in the new ‘SUMP PUMP’ logic analyzer development form. Jack has already posted a power estimate for the FPGA, and Ian has some thoughts on interface design. Maybe someone can suggest a name?

sump-dataii

This is an updated guide to the Bus Pirate logic analyzer mode, it expands on the initial documentation posted earlier.

Bus Pirate firmware v3.0 introduced a logic analyzer mode that works with the SUMP open source logic analyzer client. The logic analyzer can record 4096 samples at up to 1MHz, each channel has a selectable sample trigger.

***BIG WARNING*** The Bus Pirate will never be a substitute for a ‘proper’ logic analyzer, the hardware isn’t designed for it. The Bus Pirate can’t store a lot of samples, it can’t feed live samples very fast, and speeds are in the kHz range, not MHz.

Despite the limitations of the Bus Pirate hardware, the logic analyzer worked well enough to examine decoded IR remote signals. It’s also well suited to debug environments where you can control the bus speed (and the Bus Pirate may already be connected for other reasons). It should also be able to look at most I2C traffic (400kHz clock).

Documentation below. There’s still time to get a Bus Pirate v3, $30 including worldwide shipping.

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hvr1600tp-300x225

Check out this epic battle between man and I2C EEPROM. Devin wanted to fix a bug in the Linux driver for his HVR-1600 TV tuner card. He suspected that the Linux driver didn’t configure the board correctly, so he sniffed the I2C-based configuration traffic under Windows with a Saleae Logic. There’s a great overview of his process, including identifying test points, using them, and  filtering the traffic with a Perl script.

This showed up in our referrers list because of a link in a comment, so all thanks go to andrea venturi for this tip!

Updated, forgot the link.

sump

Today we played with a few open source logic analyzer clients in preparation for an upcoming prototype. The best we found is SUMP, written in Java. There’s also compatible host software for several FPGA development boards, we found even more ports floating around the web.

SUMP has a SourceForge page, but it doesn’t look very active. Jack Gassett’s ButterFly Platform has a SUMP compile for Windows that doesn’t require you to install the complete Java framework. You’ll also need the rxtx Java library for your platform.

Do you know of any other clients or SUMP resources?