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Openbench Logic Sniffer is an open source logic analyzer. It’s designed to support the SUMP logic analyzer software at the lowest possible cost. Download the source and design files from the Gadget Factory project page.
This project started in the comments on a post. Initial circuit design, PCB layout, development, and testing continued in the forum under the code name Project SUMP PUMP. Many, many people contributed ideas and advice, the Gadget Factory and Dangerous Prototypes coordinated circuit development and routed the PCB. We borrowed heavily from the Gadget Factory’s Butterfly Platform.
The Open Logic Sniffer is a purpose-built logic analyzer board designed to be low cost but high speed. It sacrifices a lot of the features you’d look for in a full-scale development board to achieve our primary goals:
- 70MHz+ sample speeds
- 32 channels
- 16 buffered, 5volt tolerant channels
- USB interface, USB powered
- USB upgradable everything
- Make it as DIY as possible
- Make it as open source as possible
- $30-$40 price range
We didn’t quite hit our initial price range, but we got really close.
You can get your own assembled Open Logic Sniffer at Seeed Studio for $45, including worldwide shipping. Continue reading about the design and collaboration below.
Today we completed an initial PIC firmware for the open source logic analyzer. The PIC has two operating modes: a serial bridge for SUMP to talk to the client on the FPGA, and a ROM programmer that updates the AT45DB041D flash chip with new logic for the FPGA. There’s still some bugs, but the design is coming together. Give your suggestions and follow our progress in the forum.
Major to dos:
- Finish the USB bootloader port to 18f24j50
- Clean and comment the PIC source
- Clean up the PERL updater scripts
A few months ago we started working with the Gadget Factory to build an open source logic analyzer. After a very successful collaboration, we’re almost ready to order the first PCBs. Click here for a large PCB image [PNG].
The draft device has 16 buffered (5volt tolerant) input channels, and 16 unbuffered I/O channels on a wing header. The PC connection is USB 2.0 with a PIC18F24J50 microcontroller. Both the PIC and the FPGA firmware will be USB upgradable.
You can follow our most recent progress in the forum. Uwe’s block diagram of the final design follows.
Merve is working on an Arduino-driven logic analyzer design in the Arduino Forum. It uses logic chips to drive SRAM memory during acquisition, the Arduino then dumps samples from the SRAM via a shift register.
We’re really interested in the result of this design. We once attempted a logic chip-based analyzer, but the design got complicated at high speeds because of the need for 16bit+ synchronous counters to drive the SRAM. Instead, we moved to CPLDs to try and squeeze all the logic ICs into a single, reprogrammable chip.
Several readers submitted a link to this post, thanks for the tip!
Read our goals and specs after the break.
This is an updated guide to the Bus Pirate logic analyzer mode, it expands on the initial documentation posted earlier.
Bus Pirate firmware v3.0 introduced a logic analyzer mode that works with the SUMP open source logic analyzer client. The logic analyzer can record 4096 samples at up to 1MHz, each channel has a selectable sample trigger.
***BIG WARNING*** The Bus Pirate will never be a substitute for a ‘proper’ logic analyzer, the hardware isn’t designed for it. The Bus Pirate can’t store a lot of samples, it can’t feed live samples very fast, and speeds are in the kHz range, not MHz.
Despite the limitations of the Bus Pirate hardware, the logic analyzer worked well enough to examine decoded IR remote signals. It’s also well suited to debug environments where you can control the bus speed (and the Bus Pirate may already be connected for other reasons). It should also be able to look at most I2C traffic (400kHz clock).
Documentation below. There’s still time to get a Bus Pirate v3, $30 including worldwide shipping.
We wanted to check the remote control output while we debugged the color changing pumpkin. Usually we’d use a Saleae Logic, but instead we made an experimental logic analyzer firmware for the Bus Pirate.
***BIG WARNING*** The Bus Pirate will never be a substitute for a ‘proper’ logic analyzer, the hardware isn’t designed for it. The Bus Pirate can’t store a lot of samples, it can’t feed live samples very fast, and speeds will be in the kHz, not MHz. This test firmware records 4096 samples at a fixed 10kHz sampling rate.
Despite the limitations of the Bus Pirate hardware, our logic analyzer worked well enough to examine decoded IR remote signals. It’s also well suited to debug environments where you can control the bus speed (and the Bus Pirate may already be connected for other reasons).
We’re releasing the logic analyzer as a separate firmware for v2go and v3 only, but once it’s improved we plan to integrate it into the trunk. Documentation below.
There’s still time to get a Bus Pirate v3, $30 including worldwide shipping.
Today we played with a few open source logic analyzer clients in preparation for an upcoming prototype. The best we found is SUMP, written in Java. There’s also compatible host software for several FPGA development boards, we found even more ports floating around the web.
SUMP has a SourceForge page, but it doesn’t look very active. Jack Gassett’s ButterFly Platform has a SUMP compile for Windows that doesn’t require you to install the complete Java framework. You’ll also need the rxtx Java library for your platform.
Do you know of any other clients or SUMP resources?