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Openbench Logic Sniffer is an open source logic analyzer. It’s designed to support the SUMP logic analyzer software at the lowest possible cost. Download the source and design files from the Gadget Factory project page.

This project started in the comments on a post. Initial circuit design, PCB layout, development, and testing continued in the forum under the code name Project SUMP PUMP. Many, many people contributed ideas and advice, the Gadget Factory and Dangerous Prototypes coordinated circuit development and routed the PCB. We borrowed heavily from the Gadget Factory’s Butterfly Platform.

The Open Logic Sniffer is a purpose-built logic analyzer board designed to be low cost but high speed. It sacrifices a lot of the features you’d look for in a full-scale development board to achieve our primary goals:

  • 70MHz+ sample speeds
  • 32 channels
  • 16 buffered, 5volt tolerant channels
  • USB interface, USB powered
  • USB upgradable everything
  • Make it as DIY as possible
  • Make it as open source as possible
  • $30-$40 price range

We didn’t quite hit our initial price range, but we got really close.

You can get your own assembled Open Logic Sniffer at Seeed Studio for $45, including worldwide shipping. Continue reading about the design and collaboration below.

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We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. The project is currently known by the code name ‘SUMP-PUMP’, but you can help suggest a name. The design incorporates elements of the Butterfly platform, which is available now at the Gadget Factory.

Jack finished a bunch of tests on the first SUMP PUMP build, check out the pictures and screen shots.

We’ve got the PIC firmware working, but there’s still an issue with the bootloader. You can follow our progress and make suggestions in the forum.

Today we completed an initial PIC firmware for the open source logic analyzer. The PIC has two operating modes: a serial bridge for SUMP to talk to the client on the FPGA, and a ROM programmer that updates the AT45DB041D flash chip with new logic for the FPGA. There’s still some bugs, but the design is coming together. Give your suggestions and follow our progress in the forum.

Major to dos:

  • Finish the USB bootloader port to 18f24j50
  • Clean and comment the PIC source
  • Clean up the PERL updater scripts

We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. Gerbers will go to the board house before the end of this week.

Until now we’ve called this project by the codename ‘SUMP PUMP’, because it’s a data pump for the open source SUMP logic analyzer client. This name is far to clever though, because SUMP infringes on the name of the original project, and it won’t index well in search engines.

We’d like to hear your suggestions for a name for this project. If we choose your name, we’ll send you the final hardware for free. Post your suggestions here, or in the forum.

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A few months ago we started working with the Gadget Factory to build an open source logic analyzer. After a very successful collaboration, we’re almost ready to order the first PCBs. Click here for a large PCB image [PNG].

The draft device has 16 buffered (5volt tolerant) input channels, and 16 unbuffered I/O channels on a wing header.  The PC connection is USB 2.0 with a PIC18F24J50 microcontroller. Both the PIC and the FPGA firmware will be USB upgradable.

You can follow our most recent progress in the forum. Uwe’s block diagram of the final design follows.

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We’re really excited to be joined by Jack Gassett, developer of the Butterfly FPGA platform, to prototype an open source, high-speed, low-cost logic analyzer. This effort grew out of a bunch of great comments on a post about open source logic analyzer clients.

Share your ideas for the logic analyzer in the new ‘SUMP PUMP’ logic analyzer development form. Jack has already posted a power estimate for the FPGA, and Ian has some thoughts on interface design. Maybe someone can suggest a name?


Today we played with a few open source logic analyzer clients in preparation for an upcoming prototype. The best we found is SUMP, written in Java. There’s also compatible host software for several FPGA development boards, we found even more ports floating around the web.

SUMP has a SourceForge page, but it doesn’t look very active. Jack Gassett’s ButterFly Platform has a SUMP compile for Windows that doesn’t require you to install the complete Java framework. You’ll also need the rxtx Java library for your platform.

Do you know of any other clients or SUMP resources?